Efficient Memory Organization for DNN Hardware Accelerator Implementation on PSoC

The use of deep learning solutions in different disciplines is increasing and their algorithms are computationally expensive most cases. For this reason, numerous hardware accelerators have appeared to compute operations efficiently parallel, achieving higher performance lower latency. These need large amounts data feed each computing layers, which makes it necessary handle the transfers that collect information from accelerators. implementation these accelerators, hybrid devices widely used, an embedded computer, where operating system can be run, a field-programmable gate array (FPGA), accelerator deployed. In work, we present software API organizes memory, preventing reallocating one memory area another, improves native Linux driver with 85% speed-up reduces frame time by 28% real application.